This paper introduces a more efficient embedding approach, called power consumption aware and coordinated VNE heuristic, denoted as (PaCoVNE). It embeds both virtual nodes and edges, simultaneously, and within one stage, while satisfying: CPU, BW constraints, minimizes power consumption of whole substrate network, and considers end-to- end delay as a major constraint. Performance of the new heuristic was compared to the energy aware algorithm OCA/EA-RH, for off-line scenario using homogeneous configurations, with and without end-to-end delay. The paper also presents simulation results for the two configurations once without end-to-end delay, and also when it was included.